1. Field of the Invention
The present invention relates to a fabricating method for thin film transistor array substrate and thin film transistor array substrate using the same, and more particularly, to a method of fabricating a thin film transistor array substrate and a thin film transistor array substrate using the same that may prevent picture quality degradation.
2. Discussion of the Related Art
A liquid crystal display device controls the light transmittance of liquid crystal matter using an electric field to thereby display a picture. Liquid crystal display devices may be classified into a vertical electric field type and a horizontal electric field type depending upon the direction of the electric field driving the liquid crystal.
The vertical electric field type drives liquid crystal in a TN (Twisted Nematic) mode with a vertical electric field occurring between a pixel electrode and a common electrode which oppose each other on upper and lower substrates. The vertical electric field type advantageously has large aperture ratio but has a narrow viewing angle of about 90°.
The horizontal electric field type drives liquid crystal in an In Plane Switching (hereinafter, referred to as “IPS”) mode with a horizontal electric field occurring between the pixel electrode and the common electrode arranged in parallel to each other on the lower substrate. The liquid crystal display device of IPS mode has an advantage of a wide viewing angle of about 160°.
Hereinafter, the liquid crystal display device of horizontal electric field type will be described in detail as follows.
FIG. 1 is a plan view showing a thin film transistor array substrate of a related art liquid crystal display device of horizontal electric field type, and FIG. 2 is a cross sectional view of the thin film transistor array substrate taken along the lines I-I′, II-II′ and III-III′ in FIG. 1.
Referring to FIG. 1 and FIG. 2, the thin film transistor (hereinafter, referred to as “TFT”) array substrate of the related art liquid crystal display device of horizontal electric field type comprises a gate line 2 and a data line 4 provided on a lower substrate 42 in such a manner to intersect each other with a gate insulating film 44 therebetween, a TFT 6 provided at each intersection of the gate line 2 and the data line 4, a pixel electrode 18 and a common electrode 22 formed in such a manner to provide a horizontal electric field at a pixel area having a crossing structure of the gate line 2 and the data line 4, and a common line 20 connected to a common electrode 22. The TFT array substrate further includes a gate pad 26 connected to the gate line 2 and a data pad 34 connected to the data line 4.
The TFT 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, a drain electrode 12 connected to a pixel electrode 18 and an active layer 14 for forming a channel between the source electrode 10 and the drain electrode 12. The active layer 14 may overlap with a lower data pad electrode 36, the data line 4, the source electrode 10 and the drain electrode 12. An ohmic contact layer 48 for making ohmic contact with the source electrode 10 and the drain electrode 12 is further formed on the active layer 14. Such a thin film transistor 6 allows a pixel voltage signal applied to the data line 4 to be charged into the pixel electrode 18 and kept in response to a gate signal applied to the gate line 2.
The pixel electrode 18 is connected, via a first contact hole 16 passing through a protective film 50, to the drain electrode 12 of the TFT 6. Such a pixel electrode 18 may comprise a first and second horizontal portion 18a and 18b connected to the drain electrode 12 and substantially parallel to the adjacent gate line 2, and a finger portion 18c formed between the first horizontal portion 18a and the second horizontal portion 18b. 
The common line 20 is substantially parallel to the gate line 2 and supplies a reference voltage for driving of a liquid crystal to the common electrode 22.
The common electrode 22 may be comprised of a horizontal portion 24a substantially parallel to the common line 20, and a vertical portion 22b substantially between the horizontal portion 24a and the common line 20 and provides a horizontal electric field along with the finger portion 18c of the pixel electrode 18.
Accordingly, if a pixel voltage signal is supplied, via the TFT, to the pixel electrode 18 and a reference voltage is supplied, via the common line 20, to the common electrode 22, then a horizontal electric field is formed between the finger portion 18c of the pixel electrode 18 and the vertical portion 22b of the common electrode 22. This liquid crystal display device rotates liquid crystal molecules positioned between the thin film transistor array substrate and the color filter array substrate owing to a dielectric anisotropy and transmits light inputted, via the pixel electrode 18, from a back light (not shown) toward the upper substrate to thereby display a picture.
The gate line 2 is connected, via a gate pad 26, to a gate driver (not shown). The gate pad 26 is comprised of a lower gate pad electrode 28 extending from the gate line 2 and an upper gate pad electrode 32 connected, via a second contact hole 30 passing through the gate insulating film 44 and the protective film 50, to the lower gate pad electrode 28.
The data line 4 is connected, via a data pad 34, to a data driver (not shown). The data pad 34 is comprised of a lower data pad electrode 36 extending from the data line 4 and an upper data pad electrode 40 connected, via a third contact hole 38 passing through the protective film 50, to the lower data pad electrode 36.
The TFT array substrate having such a structure is formed by a four-round mask process. This will be schematically described as follows.
First, gate patterns including the gate line 2, the gate electrode 8, the lower gate pad electrode 28, the common line 20 and the common electrode 22 are formed in a first mask process. A semiconductor pattern including the active layer 14 and the ohmic contact layer 48, and source/drain patterns such as the lower data pad electrode 36 and the source/drain electrodes 10 and 12, etc., are sequentially formed on the gate insulating film 44 entirely provided onto the lower substrate 42 in a second mask process. The protective film 50 including a first to third contact holes 16, 30 and 38 is formed in a third mask process. The pixel electrode 18, the upper gate pad electrode 32 and the upper data pad electrode 40 are formed in a fourth mask process.
In such a method of fabricating the related art TFT array substrate, the source/drain pattern and the semiconductor pattern is simultaneously formed by a diffractive mask, so that line widths of the active layer 14 and the ohmic contact layer 48 are substantially wider than those of the source electrode 10 and the drain electrode 12.
This will be described in detail with reference to FIG. 3A to FIG. 3E showing sequentially a portion of the second mask process as follows.
Referring to FIG. 3A, the gate insulating film 44, an amorphous silicon layer 14a, an amorphous silicon layer doped with an n+ impurity 48a, a source/drain metal layer 10a and a photo-resist 55 are sequentially formed on the lower substrate 42 provided with a gate pattern including the gate electrode 8, a gate line (not shown) and a gate pad by a deposition technique such as a Plasma Enhanced Chemical Vapor Deposition (PECVD) and sputtering, etc. A shielding portion is formed at an area corresponding to the source electrode 10 and the drain electrode 12 and a diffractive exposure mask having a diffractive exposure portion at an area corresponding to a channel of the thin film transistor is aligned onto the lower substrate 42.
Next, a photo-resist pattern 55a having a step coverage is formed on the source/drain metal layer 10a by a photolithography process using a second mask shown in FIG. 3B. The second mask employs a diffractive exposure mask having a diffractive exposure portion at an area corresponding to a channel of the TFT 6, so that the photo-resist pattern 55a formed at the channel of the TFT 6 may have a height lower than that of the photo-resist pattern 55a formed on the source/drain pattern.
Next, the source/drain metal layer 10a is patterned by a wet-etching process using the photo-resist pattern 55a as a mask to thereby provide the source/drain pattern including the data line 4, the source electrode 10 and the drain electrode 12 integral to the source electrode 10 shown in FIG. 3C.
The amorphous silicon layer 48a is patterned by a dry-etching process using the same photo-resist pattern 55a at the same time to thereby provide a semiconductor pattern including the ohmic contact layer 14 and the active layer 48.
Next, an ashing process is carried out, the photo-resist pattern 55a having a relatively low height at the channel of the TFT 6 is partially removed to thereby provide a photo-resist pattern 55a for exposing the source/drain metal corresponding to the channel of the TFT 6 as shown in FIG. 3D.
Herein, an ashing gas has a ratio of O2 and SF6 of about 20:1. But, if the photo-resist pattern 55a is ashed by such an ashing gas, then a thickness of the photo-resist pattern 55a as well as an edge A of the photo-resist pattern 55a is partially removed as shown in FIG. 3E. Accordingly, the photo-resist pattern 55a after the ashing process is carried out exposes an edge of the source/drain metal layer 10a. 
And then, the source/drain pattern and the ohmic contact layer 48 of the channel of the TFT 6 exposed by the remaining photo-resist pattern 55a are etched by the dry-etching process. Thus, the active layer 14 is exposed to thereby separate the source electrode 10 from the drain electrode 12. Herein, the channel of the TFT 6 is formed and the edge A of the source/drain metal layer 10a is also etched, so that the line widths of the active layer 14 and the ohmic contact layer 48 are substantially wider than that of the source/drain pattern.
The photo-resist pattern 55a remaining on the source/drain pattern is removed by a stripping process to thereby provide the source electrode 10 and the drain electrode 12, and the ohmic contact layer 48 and the active layer 14 positioned at the lower portions of the source electrode 10 and the drain electrode 12.
The method of fabricating the related art TFT array substrate simultaneously forms the semiconductor pattern, the source electrode 10 and the drain electrode 12 using the diffractive exposure mask as a second mask, so that line widths of the active layer 14 and the ohmic contact layer 48 are substantially wider than those of the source electrode 10 and the drain electrode 12.
Accordingly, an area exists where the thin film patterns such as the gate electrode 8 and the gate line 2, where light is not shielded exists at a lower portion of the active layer 14 widely provided at lower portions of the source electrode 10 and the drain electrode 12, so that light irradiated from the back light is directly irradiated into the active layer 14.
Herein, if light is irradiated onto the active layer 14, then the active layer 14 is activated by the irradiated light to thereby create a channel, so that current flows into the TFT 6. Specially, if the active layer 14 provided at the lower drain electrode 12 of the TFT 6 is activated by the irradiated light, then the TFT 6 forms a channel by the activated active layer 14 such that the TFT 6 is not turned-on by a gate signal. In other words, the TFT 6 forms the channel regardless of driving of the TFT array substrate. Accordingly, a problem results in that current charged into the pixel electrode 18 by the channel regardless of driving of the TFT array substrate is leaked to the liquid crystal display device. Thus, picture quality of the liquid crystal display device may be deteriorated by current leakage.